 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| S6B33A2 128 RGB Segment & 129 Common Driver For 4,096 Color STN LCD Sep. 06. 2002. Ver. 1.3 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version 0.0 Original 1. Page11 Added & Changed Test Pin 2. Page24 Deleted "Data Bus Mode Set" Instruction Deleted "Driving Current Mode & Bias Set" Instruction Deleted "Row Vector Mode Set" Instruction Added "DDRAM Burst Mode On/Off" Instruction 3. Page25 Deleted "Data Bus Mode Set" description 4. Page26 Reduced bus bandwidth of DIV(1) and DIV(2) 5. Page28 Deleted "Driving Current Mode and Bias Set" description 6. Page33 Deleted "Row Vector Mode Set" description Added "DDRAM Burst Mode On/Off" description 7. Page37 Deleted "MDI" bit in "Entry Mode Set" parameters 8. Page49 - Modified the register list and parameters according to modification - Page2 Deleted C24+, C24- pin in block diagram 2.Page 9 Deleted C24+, C24- pin in pin description 3.Page12 - Deleted "REG_ENB" pin - Deleted "TEST2", "TEST3" pin 4.Page23 - Delete "REG_ENB" pin on figure20 5.Page25 Added "Red, Green and Blue Palette Set" instruction. 6.Page 28 Changed DCDC clock division ratio 7.Page 35 Added "GSM" bit for gray scale selection at "Gray Scale Mode Set" instruction Page 37 Added "Red, Green and Blue Palette Set" description Page38 Added "HL" bit at "Entry Mode Set" instruction Page 50 Modified the register list and parameters according to modification 11.Page 54 Changed Oscillator frequency tolerance and range 12.Page41,43,44,55,56 - The duty of partial mode1 is changed from 1/69 to 1/66 Content Date Oct. 2001 0.1 Nov. 2001 0.2 Dec. 2001 2 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version Content - Page4~9 Added key coordinates, pad dimension, configuration and coordinates 2. Page59 Added "the limitation of usage of analog circuit" in detail 3. Page65~66 - Added system application diagram 1. Page3 Deleted CK Pin 2. Page10 Modified pin description 3. Page16 - Collected the code of X,Y address 4. Page 50 - Described write/read data which is accessed by MCU I/F in 256 color mode 1. Page5 - Deleted *note about ILB, TOM align key - Page26, 50 - Added display format select command(60H/61H) 2. Page27 Added "DIV2" bit at "Oscillation Mode Set" instruction 3. Page66 - Add maximum rating voltage of capacitors - Page 26,35,36 - Delete Burst mode on/off instruction 2. Page 59,60 - Add MPU 68/80 Parallel I/F AC Timing 1. Page 65 - Add shot-key diode at application circuit 1. Page 26, 35, 51 - Add ROW Vector Mode Set Command 1. Page 65 - Add Values of Schottky barrier diode. 1. Page 30 - Corrected Miss-typing. 1. Page 53~61 - Filled TBD items 1. Page 18 - Delete "Block NO" on figure15. 2. Page 59-60 - Delete a word of "25C" from condition item on table17. 3. Page 54 - Add DC Spec of DC2IN, VIN2 and VIN45 4. Page 55 - Add Current Measure data Date 0.3 Jan. 2002 0.4 Jan. 2002 0.5 Jan.2002 0.6 Mar.2002 0.7 May.2002 0.8 0.9 1.0 1.1 1.2 May.2002 May.2002 Jun.2002 Jul.2002 Jul.2002 1.3 Sep.2002 3 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD CONTENTS INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 PAD CONFIGURATION ................................................................................................................................. 4 PIN CONFIGURATION................................................................................................................................... 6 PAD CENTER COORDINATES ...................................................................................................................... 7 FUNCTIONAL DESCRIPTION .......................................................................................................................13 MPU INTERFACE ..................................................................................................................................13 DISPLAY DATA RAM .............................................................................................................................16 INSTRUCTION PARAMETE R .................................................................................................................49 SPECIFICATIONS .........................................................................................................................................52 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................52 OPERATING VOLTAGE .........................................................................................................................52 DC CHARACTERISTICS (1) ...................................................................................................................53 DC CHARACTERISTICS (2) ...................................................................................................................54 DC CHARACTERISTICS (3) ...................................................................................................................55 DC CHARACTERISTICS (4) ...................................................................................................................56 DC CHARACTERISTICS (5) ...................................................................................................................57 AC CHARACTERISTICS .........................................................................................................................58 4 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INTRODUCTION S6B33A2 is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. With onchip RC oscillator circuit, the display-timing signal is generated without being sent from MPU. Also, it is capable of using 8bit/16bit data bus alternatively and operating with 68/80-series MPU in asynchronous. Due to the internal bitmap display RAM of 128 x128 x12-bit, S6B33A2 is capable of operating max. 128 RGB x 128 dot LCD panels in low-power consumption. Being the segment RGB 3-output, one pixel is 12-bit data and S6B33A2 can display 4,096 color. FEATURES Driver Output - - - 129 COM X 128 RGB SEG Gray Scale Function 4,096 color display of R: 16 gray scale, G: 16 gray scale, B: 16 gray scale 256 color display of R: 8 gray scale, G: 8 gray scale, B: 4 gray scale On-chip Display Data RAM - - - - - Capacity: 128 x 128 x 12 = 196,608 bits Display Mode Normal display mode: Entire duty displaying Partial display mode: Partial displaying Standby mode: Internal display clocks off Area scroll mode: Particular area scrolling Microprocessor Interface - - 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series 3/4 Pin SPI (only write operation) On-chip Low Power Analog Circuit - - - - - - On-chip RC oscillator (Internal cap. & external resistor), external clock available Voltage converter Voltage regulator Voltage follower On-chip electronic contrast control (256 steps) Bias ratio: 1/6 Operating Voltage Range - - - - VDD : 1.8 to 3.3 [V] (without Internal Regulator), 2.4 to 3.3 [V] (With internal Regulator) VIN1: 2.4 to 3.6 [V] Display operating voltage(V1): 2.0 to 3.3 V LCD Operating Voltage Range : 20 V Low Power Consumption 650 uA Typ. Package Type COG 1 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Output Pad Pitch 38um Min. 2 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD BLOCK DIAGRAM SEGA0 SEGA127 SEGB0 - - SEGB127 COM0 - - - COM128 SEGC0 SEGC127 VDD VDD1 VSS VCC V1 VM V0 VEE VIN45 VOUT45 C11+ C11C12C12+ VIN1 VIN2 V1OUT V1T INTRS VMOUT DC2OUT SEG Driving Circuit COM Driving Circuit Oscillator Circuit OSC1 OSC2 OSC3 OSC4 OSC5 384 Decoder Circuit 1536 129 CDIR CL FR DC2IN C21+ C21C22+ C22C23+ C23- Voltage Converter/ Voltage Regulator/ Voltage Follower Display data RAM 128 X 1536 LCD System Control Circuit PM I/O Buffer X - Address Control Circuit Y - Address Control Circuit Bus Holder DC3IN C31+ C31+VR MPU System Control Circuit MPU INTERFACE -VR /CS1 CS2 D/I /RD /WR MPU[1:0] PS /RST DB<15:0> REG_OUT Power Regulator Circuit Instruction Decoder Status Figure 1. Block Diagram 3 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PAD CONFIGURATION 652 653 ....................... .. Y X 230 229 (0,0) S6B33A2 704 1 : Bump Key : ILB Align Key : COG Align Key : COF Align Key : TOM ............ . PAD 178 177 Figure 2. S6B33A2 Chip Pad Configuration Table 1. S6B33A2 Pad Dimensions Item Chip size Pad pitch Pad No. 1 ~ 177 178 to 229, 230 to 652, 653 to 704 1 ~ 177 Bumped pad size Bumped pad height 178 to 229, , 653 to 704 230 to 652 All Pad 70 170 23 17 Size X 16670 90 38 70 23 170 m Y 2430 Unit 4 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Figure 3. Bump, COG Align Key Coordinate 30m 30m 30m 30m 30m 30m 30m 42m Figure 4. ILB Align Key Coordinate 108m 108m 42m 30m 30m 30m 108 m 108m (7495,-725) 60m (-7374,740) 42m 42 m (-7500,-785) (7340,665) 50m 50m 20m (-7975,820) (7975,820) Figure 5. COF Align Key Coordinate 220um (-6785, 545) 220um (7120, 545) 580um (-7005, -35) Left (6900, -35) Right Figure 6. TOM Coordinate 5 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PIN CONFIGURATION COM45 COM46 COM47 COM0 COM1 COM2 : : : : : : : : : : : : COM48 COM49 COM50 : : : COM60 COM61 COM62 SEGC0 SEGB0 SEGA0 SEGC1 SEGB1 SEGA1 SEGC2 SEGB2 SEGA2 : : : : : : : : : : : : : : : : : : : : : : : : : : SEGC125 SEGB125 SEGA125 SEGC126 SEGB126 SEGA126 SEGC127 SEGB127 SEGA127 COM128 COM127 COM126 : : : COM113 COM112 COM111 COM110 COM109 108 : : : : : : : : : : : : COM65 COM64 COM63 VOIN VCC VRP C31P C31M VEE VRN C24M C24P C23M C23P C22M C22P C21M C21P DC2IN DC2OUT VMIN VMOUT V1T V1OUT V1IN C12M C12P C11M C11P VOUT45 VIN45 VIN2 VIN1 VDD REG_OUT VDD1 OSC1 OSC2 OSC3 OSC4 OSC5 INTRS VSS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RDB WRB RS RSTB PM FR CL TEST0 TEST1 TEST2 TEST3 TEST4 CS2 CS1B CDIR MPU0 MPU1 PS VOIN Figure 7. S6B33A2 Chip Pin Configuration S6B33A2 (Top View) 6 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PAD CENTER COORDINATES Table 2. Pad Center Coordinates [Unit: m] NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 NAME DUMMY DUMMY V0IN V0IN VSS PS VDD MPU<1> VSS MPU<0> VDD CDIR VSS CS1B CS2 TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> VDD CL FR PM RSTB RS VSS WRB RDB VDD DB<0> DB<1> DB<2> DB<3> DB<4> DB<5> DB<6> DB<7> DB<8> DB<9> DB<10> DB<11> DB<12> DB<13> DB<14> DB<15> VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X -7920 -7830 -7740 -7650 -7560 -7470 -7380 -7290 -7200 -7110 -7020 -6930 -6840 -6750 -6660 -6570 -6480 -6390 -6300 -6210 -6120 -6030 -5940 -5850 -5760 -5670 -5580 -5490 -5400 -5310 -5220 -5130 -5040 -4950 -4860 -4770 -4680 -4590 -4500 -4410 -4320 -4230 -4140 -4050 -3960 -3870 -3780 -3690 -3600 -3510 -3420 -3330 -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 Y -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 NO 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 NAME VSS VSS VSS VDD INTRS OSC5 VSS OSC4 OSC3 OSC2 OSC1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 REG_OUT REG_OUT REG_OUT VDD VDD VDD VDD VDD VDD VDD VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN2 VIN2 VIN2 VIN2 VIN45 VIN45 VOUT45 VOUT45 C11P C11P C11P C11M C11M C11M C12P C12P C12P C12M C12M C12M V1IN V1IN X -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620 -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 2160 2250 2340 2430 2520 2610 2700 2790 Y -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 NO 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NAME V1OUT V1OUT V1T VMOUT VMOUT VMOUT VMIN VMIN VMIN DC2OUT DC2OUT DC2IN DC2IN C21P C21P C21P C21M C21M C21M C22P C22P C22P C22M C22M C22M C23P C23P C23P C23M C23M C23M VRN VRN VRN VEE VEE VEE VEE DUMMY C31M C31M C31M DUMMY C31P C31P C31P DUMMY VRP VRP VCC VCC DUMMY VSS V0IN V0IN DUMMY DUMMY DUMMY DUMMY COM<0> X 2880 2970 3060 3150 3240 3330 3420 3510 3600 3690 3780 3870 3960 4050 4140 4230 4320 4410 4500 4590 4680 4770 4860 4950 5040 5130 5220 5310 5400 5490 5580 5670 5760 5850 5940 6030 6120 6210 6300 6390 6480 6570 6660 6750 6840 6930 7020 7110 7200 7290 7380 7470 7560 7650 7740 7830 7920 8165 8165 8165 Y -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1069 -1031 -993 NO 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 NAME COM<1> COM<2> COM<3> COM<4> COM<5> COM<6> COM<7> COM<8> COM<9> COM<10> COM<11> COM<12> COM<13> COM<14> COM<15> COM<16> COM<17> COM<18> COM<19> COM<20> COM<21> COM<22> COM<23> COM<24> COM<25> COM<26> COM<27> COM<28> COM<29> COM<30> COM<31> COM<32> COM<33> COM<34> COM<35> COM<36> COM<37> COM<38> COM<39> COM<40> COM<41> COM<42> COM<43> COM<44> COM<45> COM<46> COM<47> DUMMY DUMMY DUMMY DUMMY COM<48> COM<49> COM<50> COM<51> COM<52> COM<53> COM<54> COM<55> COM<56> X 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8165 8018 7980 7942 7904 7866 7828 7790 7752 7714 7676 7638 Y -955 -917 -879 -841 -803 -765 -727 -689 -651 -613 -575 -537 -499 -461 -423 -385 -347 -309 -271 -233 -195 -157 -119 -81 -43 -5 33 71 109 147 185 223 261 299 337 375 413 451 489 527 565 603 641 679 717 755 793 831 869 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 7 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: m] NO 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 NAME COM<57> COM<58> COM<59> COM<60> COM<61> COM<62> DUMMY SEGC<0> SEGB<0> SEGA<0> SEGC<1> SEGB<1> SEGA<1> SEGC<2> SEGB<2> SEGA<2> SEGC<3> SEGB<3> SEGA<3> SEGC<4> SEGB<4> SEGA<4> SEGC<5> SEGB<5> SEGA<5> SEGC<6> SEGB<6> SEGA<6> SEGC<7> SEGB<7> SEGA<7> SEGC<8> SEGB<8> SEGA<8> SEGC<9> SEGB<9> SEGA<9> SEGC<10> SEGB<10> SEGA<10> SEGC<11> SEGB<11> SEGA<11> SEGC<12> SEGB<12> SEGA<12> SEGC<13> SEGB<13> SEGA<13> SEGC<14> SEGB<14> SEGA<14> SEGC<15> SEGB<15> SEGA<15> SEGC<16> SEGB<16> SEGA<16> SEGC<17> SEGB<17> X 7600 7562 7524 7486 7448 7410 7372 7334 7296 7258 7220 7182 7144 7106 7068 7030 6992 6954 6916 6878 6840 6802 6764 6726 6688 6650 6612 6574 6536 6498 6460 6422 6384 6346 6308 6270 6232 6194 6156 6118 6080 6042 6004 5966 5928 5890 5852 5814 5776 5738 5700 5662 5624 5586 5548 5510 5472 5434 5396 5358 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 NO 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 NAME SEGA<17> SEGC<18> SEGB<18> SEGA<18> SEGC<19> SEGB<19> SEGA<19> SEGC<20> SEGB<20> SEGA<20> SEGC<21> SEGB<21> SEGA<21> SEGC<22> SEGB<22> SEGA<22> SEGC<23> SEGB<23> SEGA<23> SEGC<24> SEGB<24> SEGA<24> SEGC<25> SEGB<25> SEGA<25> SEGC<26> SEGB<26> SEGA<26> SEGC<27> SEGB<27> SEGA<27> SEGC<28> SEGB<28> SEGA<28> SEGC<29> SEGB<29> SEGA<29> SEGC<30> SEGB<30> SEGA<30> SEGC<31> SEGB<31> SEGA<31> SEGC<32> SEGB<32> SEGA<32> SEGC<33> SEGB<33> SEGA<33> SEGC<34> SEGB<34> SEGA<34> SEGC<35> SEGB<35> SEGA<35> SEGC<36> SEGB<36> SEGA<36> SEGC<37> SEGB<37> X 5320 5282 5244 5206 5168 5130 5092 5054 5016 4978 4940 4902 4864 4826 4788 4750 4712 4674 4636 4598 4560 4522 4484 4446 4408 4370 4332 4294 4256 4218 4180 4142 4104 4066 4028 3990 3952 3914 3876 3838 3800 3762 3724 3686 3648 3610 3572 3534 3496 3458 3420 3382 3344 3306 3268 3230 3192 3154 3116 3078 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 NO 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 NAME SEGA<37> SEGC<38> SEGB<38> SEGA<38> SEGC<39> SEGB<39> SEGA<39> SEGC<40> SEGB<40> SEGA<40> SEGC<41> SEGB<41> SEGA<41> SEGC<42> SEGB<42> SEGA<42> SEGC<43> SEGB<43> SEGA<43> SEGC<44> SEGB<44> SEGA<44> SEGC<45> SEGB<45> SEGA<45> SEGC<46> SEGB<46> SEGA<46> SEGC<47> SEGB<47> SEGA<47> SEGC<48> SEGB<48> SEGA<48> SEGC<49> SEGB<49> SEGA<49> SEGC<50> SEGB<50> SEGA<50> SEGC<51> SEGB<51> SEGA<51> SEGC<52> SEGB<52> SEGA<52> SEGC<53> SEGB<53> SEGA<53> SEGC<54> SEGB<54> SEGA<54> SEGC<55> SEGB<55> SEGA<55> SEGC<56> SEGB<56> SEGA<56> SEGC<57> SEGB<57> X 3040 3002 2964 2926 2888 2850 2812 2774 2736 2698 2660 2622 2584 2546 2508 2470 2432 2394 2356 2318 2280 2242 2204 2166 2128 2090 2052 2014 1976 1938 1900 1862 1824 1786 1748 1710 1672 1634 1596 1558 1520 1482 1444 1406 1368 1330 1292 1254 1216 1178 1140 1102 1064 1026 988 950 912 874 836 798 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 NO 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 NAME SEGA<57> SEGC<58> SEGB<58> SEGA<58> SEGC<59> SEGB<59> SEGA<59> SEGC<60> SEGB<60> SEGA<60> SEGC<61> SEGB<61> SEGA<61> SEGC<62> SEGB<62> SEGA<62> SEGC<63> SEGB<63> SEGA<63> SEGC<64> SEGB<64> SEGA<64> SEGC<65> SEGB<65> SEGA<65> SEGC<66> SEGB<66> SEGA<66> SEGC<67> SEGB<67> SEGA<67> SEGC<68> SEGB<68> SEGA<68> SEGC<69> SEGB<69> SEGA<69> SEGC<70> SEGB<70> SEGA<70> SEGC<71> SEGB<71> SEGA<71> SEGC<72> SEGB<72> SEGA<72> SEGC<73> SEGB<73> SEGA<73> SEGC<74> SEGB<74> SEGA<74> SEGC<75> SEGB<75> SEGA<75> SEGC<76> SEGB<76> SEGA<76> SEGC<77> SEGB<77> X 760 722 684 646 608 570 532 494 456 418 380 342 304 266 228 190 152 114 76 38 0 -38 -76 -114 -152 -190 -228 -266 -304 -342 -380 -418 -456 -494 -532 -570 -608 -646 -684 -722 -760 -798 -836 -874 -912 -950 -988 -1026 -1064 -1102 -1140 -1178 -1216 -1254 -1292 -1330 -1368 -1406 -1444 -1482 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 8 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: m] NO 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 NAME SEGA<77> SEGC<78> SEGB<78> SEGA<78> SEGC<79> SEGB<79> SEGA<79> SEGC<80> SEGB<80> SEGA<80> SEGC<81> SEGB<81> SEGA<81> SEGC<82> SEGB<82> SEGA<82> SEGC<83> SEGB<83> SEGA<83> SEGC<84> SEGB<84> SEGA<84> SEGC<85> SEGB<85> SEGA<85> SEGC<86> SEGB<86> SEGA<86> SEGC<87> SEGB<87> SEGA<87> SEGC<88> SEGB<88> SEGA<88> SEGC<89> SEGB<89> SEGA<89> SEGC<90> SEGB<90> SEGA<90> SEGC<91> SEGB<91> SEGA<91> SEGC<92> SEGB<92> SEGA<92> SEGC<93> SEGB<93> SEGA<93> SEGC<94> SEGB<94> SEGA<94> SEGC<95> SEGB<95> SEGA<95> SEGC<96> SEGB<96> SEGA<96> SEGC<97> SEGB<97> X -1520 -1558 -1596 -1634 -1672 -1710 -1748 -1786 -1824 -1862 -1900 -1938 -1976 -2014 -2052 -2090 -2128 -2166 -2204 -2242 -2280 -2318 -2356 -2394 -2432 -2470 -2508 -2546 -2584 -2622 -2660 -2698 -2736 -2774 -2812 -2850 -2888 -2926 -2964 -3002 -3040 -3078 -3116 -3154 -3192 -3230 -3268 -3306 -3344 -3382 -3420 -3458 -3496 -3534 -3572 -3610 -3648 -3686 -3724 -3762 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 NO 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 NAME SEGA<97> SEGC<98> SEGB<98> SEGA<98> SEGC<99> SEGB<99> SEGA<99> SEGC<100> SEGB<100> SEGA<100> SEGC<101> SEGB<101> SEGA<101> SEGC<102> SEGB<102> SEGA<102> SEGC<103> SEGB<103> SEGA<103> SEGC<104> SEGB<104> SEGA<104> SEGC<105> SEGB<105> SEGA<105> SEGC<106> SEGB<106> SEGA<106> SEGC<107> SEGB<107> SEGA<107> SEGC<108> SEGB<108> SEGA<108> SEGC<109> SEGB<109> SEGA<109> SEGC<110> SEGB<110> SEGA<110> SEGC<111> SEGB<111> SEGA<111> SEGC<112> SEGB<112> SEGA<112> SEGC<113> SEGB<113> SEGA<113> SEGC<114> SEGB<114> SEGA<114> SEGC<115> SEGB<115> SEGA<115> SEGC<116> SEGB<116> SEGA<116> SEGC<117> SEGB<117> X -3800 -3838 -3876 -3914 -3952 -3990 -4028 -4066 -4104 -4142 -4180 -4218 -4256 -4294 -4332 -4370 -4408 -4446 -4484 -4522 -4560 -4598 -4636 -4674 -4712 -4750 -4788 -4826 -4864 -4902 -4940 -4978 -5016 -5054 -5092 -5130 -5168 -5206 -5244 -5282 -5320 -5358 -5396 -5434 -5472 -5510 -5548 -5586 -5624 -5662 -5700 -5738 -5776 -5814 -5852 -5890 -5928 -5966 -6004 -6042 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 NO 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 NAME SEGA<117> SEGC<118> SEGB<118> SEGA<118> SEGC<119> SEGB<119> SEGA<119> SEGC<120> SEGB<120> SEGA<120> SEGC<121> SEGB<121> SEGA<121> SEGC<122> SEGB<122> SEGA<122> SEGC<123> SEGB<123> SEGA<123> SEGC<124> SEGB<124> SEGA<124> SEGC<125> SEGB<125> SEGA<125> SEGC<126> SEGB<126> SEGA<126> SEGC<127> SEGB<127> SEGA<127> DUMMY COM<128> COM<127> COM<126> COM<125> COM<124> COM<123> COM<122> COM<121> COM<120> COM<119> COM<118> COM<117> COM<116> COM<115> COM<114> COM<113> COM<112> COM<111> DUMMY DUMMY DUMMY DUMMY COM<110> COM<109> COM<108> COM<107> COM<106> COM<105> X -6080 -6118 -6156 -6194 -6232 -6270 -6308 -6346 -6384 -6422 -6460 -6498 -6536 -6574 -6612 -6650 -6688 -6726 -6764 -6802 -6840 -6878 -6916 -6954 -6992 -7030 -7068 -7106 -7144 -7182 -7220 -7258 -7296 -7334 -7372 -7410 -7448 -7486 -7524 -7562 -7600 -7638 -7676 -7714 -7752 -7790 -7828 -7866 -7904 -7942 -7980 -8018 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 Y 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 1045 869 831 793 755 717 679 641 603 NO 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 NAME COM<104> COM<103> COM<102> COM<101> COM<100> COM<99> COM<98> COM<97> COM<96> COM<95> COM<94> COM<93> COM<92> COM<91> COM<90> COM<89> COM<88> COM<87> COM<86> COM<85> COM<84> COM<83> COM<82> COM<81> COM<80> COM<79> COM<78> COM<77> COM<76> COM<75> COM<74> COM<73> COM<72> COM<71> COM<70> COM<69> COM<68> COM<67> COM<66> COM<65> COM<64> COM<63> DUMMY DUMMY X -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 -8165 Y 565 527 489 451 413 375 337 299 261 223 185 147 109 71 33 -5 -43 -81 -119 -157 -195 -233 -271 -309 -347 -385 -423 -461 -499 -537 -575 -613 -651 -689 -727 -765 -803 -841 -879 -917 -955 -993 -1031 -1069 9 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PIN DESCRIPTION Table 3. Power Supply Pins Name VDD VDD3R VDD1 VSS,VSSA VSSB,VSSO VCC V1IN VMIN V0IN VEE,VEES VIN1,VIN1A VIN2 VOUT45 VIN45 C11+ C11C12+ C12V1OUT V1T INTRS VMOUT DC2OUT DC2IN C21+ C21C22+ C22C23+ C23-VR C31+ C31+VR I/O Supply Supply Supply GND I I I I I I I O I O O I I O O I O O O O Description Power supply(Logic) Internal regulator power supply This pin is connected to VDD. Regulated power supply input pin for internal digital and DDRAM block. This pin is connected to REG_OUT outside the chip with stabilization capacitor. When the internal regulator is not used, VDD1 should be tied to VDD directly. Ground LCD common high selected driving voltage input pin LCD segment high selected driving voltage input pin LCD common/segment non-selected driving voltage input pin LCD segment low selected driving voltage input pin LCD common low selected driving voltage input pin The relationship between VCC, V1, VM, V0 and VEE: VCC > V1 > VM > V0(=VSS) > VEE (V1 - VM = VM - V0, VCC -VM = VM - VEE) Power supply for 1'st booster circuit and VM amp Power supply for 2'nd booster circuit 1'st booster output pin Power supply for V1. Connect to VOUT45 or VIN1 External capacitor connection pins used for 1'st booster circuit LCD segment high driving voltage output pin Thermistor resistor connection pin External resister select pin for temperature compensation circuit - INTRS = L : External resistor mode, INTRS = H : Internal resistor mode LCD common/segment non-selected driving voltage output pin Power output pin for 2'nd booster input Power supply for 2'nd booster. Connect to DC2OUT pin External capacitor connection pins used for 2'nd booster circuit LCD common low selected driving voltage output pin External capacitor connection pins used for 3'rd booster circuit LCD common high selected driving voltage output pin 10 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 4. MPU Interface Pins Name /RST I/O I Description Reset input pin. When /RST is "L", initialization is executed. MPU interface select pin PS H PS MPU[1:0] I H H H L L /CS1 CS2 D/I I MPU[1] L L H H L H MPU[0] L H L H X X Description 8080-series 8bit interface 8080-series 16bit interface 6800-series 8bit interface 6800-series 16bit interface 3 pin SPI(Write only) 4 pin SPI(Write only) Chip select input pins Data / instruction I/O is enabled only when /CS1 is "L" and CS2 is "H". When chip select is non-active, DB0 to DB15 may be high impedance. Data / Instruction select input pin - D/I = "H": DB0 to DB15 are display data - D/I = "L": DB0 to DB7 are instruction data Read / Write execution control pin PS MPU H MPU Type 6800-series /WR R/W Description Read/Write control input pin - R/W = "H": read - R/W = "L": write Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the /WR signal. I /WR (R/W) I H H L 8080-series /WR Read / Write execution control pin MPU[1] /RD (E) MPU type /RD Description Read / Write control input pin - R/W = "H": When E is "H", DB0 to DB15 are in an output status. - R/W = "L": The data on DB0 to DB15 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB15 are in an output status. I H 6800series E L DB[15:8] DB[7]/SDI DB[6]/SCL DB[5:0] CDIR 8080series /RD I/O I -DB[15:0]: 16-bit bi-directional data bus. -SDI: Serial data input pin. The data is latched at the rising edge of SCL. -SCL: Serial clock input pin. Common direction select pin. 11 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 5. Oscillator and Power Regulator Pins Name OSC1 OSC2 OSC3 OSC4 I/O Description CR oscillator output pin When the internal CR oscillator is used, connect to OSC1, OSC3 through a resistor. OSC1 - OSC2: Using in normal display mode, partial display mode 0 OSC3 - OSC4: Using in partial display mode 1 When an external oscillator is used, OSC1 pin is connected to VDD or VSS. External clock input pin When an external input is used, it is input to this pin. But the internal oscillator is used, this pin is connected to VDD or VSS. Internal voltage regulator output pin The regulator output port from this pin is used as a power supplier for an internal digital block via VDD1 pins. O OSC5 I REG_OUT O Table 6. Timing signal Pins for monitoring Name CL PM FR I/O O O O Shift clock output pin Field delimiter output pin Liquid crystal alternating current output pin Description Table 7. LCD driver output pins Name SEGA0 to 127 SEGB0 to 127 SEGC0 to127 COM0 to 128 I/O O O O O Description LCD driving segment output (Red or Blue) LCD driving segment output (Green) LCD driving segment output (Blue or Red) LCD common outputs Table 8. Test pins Name TEST [4:0] I/O I Description Don't use these pins. IC maker's test pins. Fix "High" in normal mode. 12 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD FUNCTIONAL DESCRIPTION MPU INTERFACE Chip Select Input There are /CS1 and CS2 pins for chip selection. The S6B33A2 can interface with an MPU only when /CS1 is "L" and CS2 is "H". When these pins are set to any other combination, D/I, /RD, and /WR inputs are disabled and DB0 to DB15 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel/Serial Interface The S6B33A2 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table9. Table 9. Parallel / Serial Interface Mode. PS MPU[1] L H H L H /CS1 CS2 6800-Series MPU 3-Pin SPI 4-Pin SPI /CS1 CS2 MPU bus type 8080-Series MPU L /CS1 CS2 Parallel Interface (PS="H") The 8-bit/16-bit bi-directional data bus is used in parallel interface. The type of MPU is selected by MPU[1] and the mode of data-bus is controlled by MPU[0] as shown in below. In accessing internal registers (D/I = "L"), only DB[7:0] are valid. Table 10. Microprocessor Selection for Parallel Int erface MPU[1] L MPU[0] L H L H /CS1 /CS1 CS2 CS2 /RD E /WR R/W Data Bus DB[7:0] DB[15:0] DB[7:0] DB[15:0] MPU bus type 8080-series MPU H /CS1 CS2 /RD /WR 6800-series MPU Table 11. Parallel Data Transfer 6800-series D/I /RD H H L L H H H H /WR H L H L /RD L H L H /WR H L H L Read display data Write display data Read out internal status register Write instruction data 8080-series Description 13 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD /CS1 CS2 D/I R/W E DB Command Write Data Write Status Read Data Read Figure 8. 6800-Series MPU Interface protocol (MPU[1]="H") /CS1 CS2 D/I /WR /RD DB Command Write Data Write Status Read Data Read Figure 9. 8080-Series MPU Interface Protocol (MPU[1]="L") Serial Interface(PS="L") Communication with the microprocessor occurs v a clock-synchronized serial peripheral interface when PS is low. ia When using the serial interface, read operations are not allowed. When the chip select inputs are valid (/CS1 = "L" & CS2 = "H"), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and processed as 8 bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. And Invalid, the internal shift register and the counter are reset. The serial interface type is selected by setting PS as shown in Table12. 14 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 12. Microprocessor Selection for Serial Interface PS L MPU[1] L H /CS1 /CS1 /CS1 CS2 CS2 CS2 D/I D/I S/W Serial Data DB[7] Serial Clock DB[6] SPI Mode 3-Pin 4-Pin 3-Pin SPI Interface (PS = "L" & MPU[1] = "L") In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length is used to indicate whether serial data input is display or instruction data instead of D/I pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists of three bytes instruction. The first byte instruction enables the next two instructions to be valid, and the data of the next two bytes indicate that a specified number of display data bytes(1 to 65536) are to be transmitted. For details, refer the Figure 8. Chip Select 1 2 /CS1 = L, CS2 = H 23 24 1 2 79 80 SCL(DB6) 2 bytes 9 bytes 9 bytes display data User's display data (Initial 50688 bytes) SDI(DB7) 11111100 DDL_SET 00000000 00001001 Internal D/I DDL_H = 0 DDL_L = 9 (Initial : 80h,00h) = 32,768 Figure 10. 3-Pin SPI Timing (D/I is not used) 4-Pin Serial Interface (PS="L" & MPU[1]="H") In 4-pin SPI interface mode, D/I pin is used for indicating whether serial data input is display or instruction data. Data is display data when D/I is high and instruction data when D/I is low. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Chip Select l /CS1=L, CS2=H DB2 SID (DB7) SCL(DB6) D/I DB7 DB6 DB5 DB4 DB3 DB1 DB0 DB7 DB7 Figure 11. 4-Pin Serial Interface Timing 15 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DISPLAY DATA RAM The on-chip display data RAM of S6B33A2 is a static RAM that is stored the data for the display. It is a 1,536x 128 structure. It is controlled by 2 addresses, X and Y. And, RAM area selection and automatic address count up functions are accomplished by the internal instructions. DDRAM Address Area Selection A part of DDRAM address area of S6B33A2 can be accessed by X and Y address area settings. After setting RAM area, the addresses become the start address. Y-address area X-address area Figure 12. DDRAM Address Area Table 13. X address Control DB7 Code P1 P2 0 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 X start address set(Initial Status = 00H) X end address set(Initial Status = 7FH) Table 14. Y address Control DB7 Code P1 P2 0 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1 Y start address set (Initial status = 00H) Y end address set (Initial status =7FH) 16 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD RAM Addressing Count up By selecting the X address and Y address area by the internal instructions, the address counts up from its start address to end address after data access operation. When one address is equal to the end address, it returns to the start address. At this time, the other address is increased by 1. Y address count mode (Y address = 00h to7Fh, X address = 00h to 7Fh, 16 bit access mode) Y-address 00 00h 01h X-address 02h 03h 0 128 256 384 01 1 02 2 03 3 04 4 05 5 06 6 07 7 08 8 7Fh 127 255 383 511 7Fh 16256 Figure 13. Y address count mode 16383 X address count mode (Y address =00h to 7Fh, X address = 00h to 7Fh, 16 bit access mode) Y-address 00h 01h X-address 02h 03h 00h 01h 02h 03h 04h 05h 06h 07h 08h 0 128 256 384 512 640 768 896 1024 1 2 3 7Fh 16256 7Fh 127 255 383 511 639 767 895 1023 1151 Figure 14. X address count mode 16383 17 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD YA Address XA Address 00H 01H 02H 03H 04H 05H 06H 07H 08H - - - - - - - 79H 7AH 7BH 7CH 7DH 7EH 7FH 00H ------01H ------02H ------03H ------04H ------05H ------06H ------07H ------08H ------09H ------0AH ------0BH ------0CH ------0DH ------0EH ------0FH ----------70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 4K color ----------------------------------------------------------------------------------------------------D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Red Green Blue Figure 15. Display Data RAM Map 18 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode The S6B33A2 realizes the partial display function with low duty driving for saving power consumption and showing the various display duties. It is set as display start/end line number. Area Scroll Function The S6B33A2 realizes the specific area scroll function. (1/128 duty case). Example of Scrolling up 0 Fixed 15 lines 14 15 100 Lines 115 Fixed 18 lines 127 Example of Scrolling down 0 14 15 LCD Panel Fixed area Scroll area Display area 115 127 Figure 16. Area scroll examples (duty = 1/128, center scroll mode) 19 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display Direction SDIR The direction of segment display is selected by SDIR which is a bit in internal register. SEGA0 SEGB0 SEGC0 Y=0 x=0 (D3~D0) (D7~D0) (D3~D0) SEGA1 SEGB1 SEGC1 Y=1 (D7~D0) SEGA127 SEGB127 9 SEGC127 Y = 127 (D3~D0) (D7~D0) 1st 2nd 1st 2nd 1st 2nd Figure 17. 8-bit data bus mode when SDIR = "0" SEGA0 SEGB0 SEGC0 Y=0 (D11~D0) SEGA1 SEGB1 SEGC1 Y=1 (D11~D0) SEGA127 SEGB127 SEGC127 Y = 127 (D11~D0) x=0 Figure 18. 16-bit data bus mode when SDIR = "0" SEGA0 SEGB0 SEGC0 Y = 127 (D3~D0) (D7~D0) (D3~D0) SEGA1 SEGB1 SEGC1 Y = 126 (D7~D0) SEGA127 SEGB127 SEGC127 Y=0 (D3~D0) (D7~D0) x=0 1st 2nd 1st 2nd 1st 2nd Figure 19. 8-bit data bus mode when SDIR = "1" SEGA0 SEGB0 SEGC0 Y = 127 (D11~D0) SEGA1 SEGB1 SEGC1 Y = 126 (D11~D0) SEGA127 SEGB127 SEGC127 Y=0 (D11~D0) x=0 Figure 20. 16-bit data bus mode when SDIR = "1" 20 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD CDIR The direction of common scanning is selected by CDIR pin. COM 62 SEG128RGB COM128 COM 0 Driver COM63 128Display Lines COM 0 Line number 0 COM 0 COM 1 Line number 127 Display Area Display Area COM 127 COM 128 Line number 127 COM 128 Line number 0 21 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SWP=1 SEGAi SEGBi * i = 0 to 127 SEGCi Gray Scale control RAM DATA MPU I/F DATA[11:0] Gray Scale control Gray Scale control D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 SWP=0 SEGAi SEGBi * i = 0 to 127 SEGCi Gray Scale control RAM DATA Gray Scale control Gray Scale control D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 MPU I/F DATA[11:0] R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 SEGAi SWP = 0 SWP = 1 RED D11 ~ D8 BLUE SEGBi GREEN D7 ~ D4 GREEN SEGCi BLUE D3 ~ D0 RED Color Assigned Bit Color Assigned Bit D3~ D0 D7 ~ D4 D11 ~ D8 Figure 21. The relationship between SEG outputs and RGB color 22 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD On-Chip Regulator Configuration Value of external Capacitance Item C1 REG_OUT C1 VDD1 VDD VDD VDD VDD1 VDD REG_OUT Floating Value 1.0 to 4.7 Unit F VDD: 2.4 ~ 3.3V VDD: 1.7 ~ 3.3V Figure 22. Regulator Application Oscillator Circuit When internal oscillator is used(EXT=0), the selection of oscillator resistor is determined by display mode. Normal display mode/ Partial display mode 0 : resistor1 between OSC1 and OSC2 Partial display mode 1 : resistor2 between OSC3 and OSC4 When external clock is used (EXT=1), clock frequency should be adjusted to display mode which is selected. Example of external oscillator application Ext. VSS When external clock mode (EXT = "H") is used, it is not possible to use the partial mode1 OSC5 OSC4 OSC3 OSC2 OSC1 Figure 23. External oscillator application 23 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Example of internal oscillator application VSS/VDD VSS/VDD R1 OSC5 OSC4 OSC3 OSC2 OSC1 OSC5 OSC4 R2 OSC3 OSC2 R1 OSC1 When partial display mode 1 is not used. When partial display mode 1 is used. Figure 24. Internal oscillator application Discharge Circuit Driving voltage level discharge time at stand by ON. T[ms] Internal STB signal +VR V1 VM V+[mV] VSS V-[mV] -VR The relation between voltage level and discharge time from when "Stand By ON" command is inputted. LEVEL +VR,V1,VM,-VR CONDITION +VR=10.5V, V1=3.0V, VM=1.5V, -VR=-7.5V at T=0 T[ms] 100 300 *V+,*V-[mV] < 50 < 20 24 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INSTRUCTION DESCRIPTION Table 15. Instruction Table Instruction Name Non Operation Oscillation Mode Set Driver Output Mode Set DC-DC Select DCDC Clock Division Set DCDC and AMP ON/OFF set Temperature Compensation Set Contrast Control(1) Contrast Control(2) Standby Mode OFF Standby Mode ON Addressing Mode Set ROW Vector Mode Set N-line Inversion Set Red palette Set Green palette Set Blue palette Set Entry Mode Set X-address Area Set Y-address Area Set Display OFF Display ON Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set Area Scroll Mode Set Scroll Start Line Set Display Format Select(Mode0) Display Format Select(Mode1) Set Display Data Length Display Data Write Display Data Read Status Read Test Mode0 Test Mode1 D/I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 0 0 0 /R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 1 1 0 0 /RD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 0 0 1 1 DB15 DB7 ~D 8 B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DB6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB5 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 DB4 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 DB3 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 DB2 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 DB1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 DB0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 Hex. Parameter 00 02 10 20 24 26 28 2A 2B 2C 2D 30 32 34 38 3A 3C 40 42 43 50 51 53 55 56 57 59 5A 60 61 FC 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 8Byte 8Byte 4Byte 1Byte 2Byte 2Byte 1Byte 1Byte 1Byte 1Byte 4Byte 1Byte 2Byte - Display Data Write Display Data Read Status Data Read * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FF FE *: Don't care Parameter: The number of parameter bytes that follows instruction data. 25 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Non Operation (00H) This instruction is Non operation. D/I /WR /RD DB7 0 0 1 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 Oscillation Mode Set (02H) Setting internal function mode. D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 0 DIV2 DB1 1 EXT DB0 0 OSC DIV2: Display clock selecting DIV2 = 0: Display clock = OSC clock (Initial status) DIV2= 1: Display clock = OSC/2 clock EXT: External clock selecting EXT = 0: Internal clock mode (Initial status) EXT = 1: External clock mode OSC: Internal oscillator ON/OFF OSC = 0: Internal oscillator OFF(Initial status) OSC = 1: Internal oscillator ON Driver Output Mode Set(10H) This instruction sets the display direction. D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 0 0 DB5 0 0 DB4 1 0 DB3 0 0 DB2 0 0 DB1 0 SDIR DB0 0 SWP SDIR: Segment direction This bit is for controlling the direction of segment driver. SDIR = 0 (Initial status) SWP: Swap segment output SEGAi and SEGCi This bit is for swapping the output of segment driver. SWP = 0 (Initial status) 26 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select (20H) Selects DC-DC step-up of the common driver in normal and partial mode D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 0 0 DB5 1 0 DB4 0 0 DB3 0 0 DB2 0 0 DB1 0 DC(2) DB0 0 DC(1) DC(1) : 1'st DC-DC booster boosting step select for V1 generation in normal mode and partial mode 0. DC(2) : 1'st DC-DC booster boosting step select for V1 generation in partial mode 1. DC(2) : In partial mode 1 DB1 0 1 DC-DC step up X1.0 X1.5 DC(1) : In normal mode, partial mode 0 DB0 0 1 DC-DC step up X1.0 X1.5 27 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select and power supply for V1 Op-Amp. Even if VIN45 is connected to VOUT45 or VIN1, a setup by software must be able to be performed. Power supply for V1 Op.Amp. is decided by Hardware setting and Software setting. The example of usage is shown below. Figure28. Example : Hardware Setting Software Setting : VIN45 connected to VOUT45 : Power supply for V1 Op.Amp. uses VIN1 ( not VOUT45). Hardware Setting VIN45 Software Setting VOUT45 + VSS C11+ C11C12+ C12EV_256 R1 Reference voltage generator & Temperature Compensation Control Circuit 1st Booster Circuit R1 V1 VIN1 V1 generation circuit Hardware setting : VIN45 connected to (1) VIN1 (when 1'st boosting is not used) (2) VOUT45 (when 1'st boosting is used) Software setting : DC-DC Select(20H) - DC(1), DC(2) Set value "00" Power supply for V1 Op.Amp. uses VIN1 directly. Set value "01" or "10" Power supply for V1 Op.Amp. uses VOUT45. 28 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DCDC Clock Division (24H) This instruction sets the internal booster clock frequency. D/I /WR /RD DB7 DB6 DB5 0 0 1 0 0 0 0 1 DIV(2) DB4 0 DB3 0 0 DB2 1 0 DB1 0 DIV(1) DB0 0 DIV(1) : DC-DC Charge Pump Division Ratio in Normal Mode Display and Partial Display Mode0 - DIV(1) = 10 (Initial status) DIV(2) : Division Ratio in Partial Display Mode1 - DIV(2) = 10 (Initial status) DB5 0 0 1 1 DB4 0 1 0 1 DIV(2) fPCK = fOSC/2x fPCK = fOSC/4x fPCK = fOSC/6x fPCK = fOSC/8x DB1 0 0 1 1 DB0 0 1 0 1 DIV(1) fPCK = fOSC/2x fPCK = fOSC/4x fPCK = fOSC/6x fPCK = fOSC/8x Note: fOSC = ( ROUNDUP (Duty/3) + dummy) x 4 x 4 x frame frequency DC/DC and AMP ON/OFF Set (26H) This instruction set up the DC/DC and Op-amp in common start up setting. D/I 0 /WR 0 /RD 1 DB7 0 DB6 0 DB5 1 0 DB4 0 0 DB3 0 AMP DB2 1 DCDC3 DB1 1 DCDC2 DB0 0 DCDC1 0 0 AMP : Built-in OP-AMP ON/OFF. - AMP=0 :OP-AMP OFF(Initial status) - AMP=1 :OP-AMP ON st DCDC1: Built-in 1 Booster ON/OFF (Initial status) st - DCDC1= 0: 1 Booster OFF (Initial status) st - DCDC1= 1: 1 Booster ON st DCDC2: Built-in 1 Booster ON/OFF (Initial status) nd - DCDC2= 0: 2 Booster OFF (Initial status) nd - DCDC2= 1: 2 Booster ON st DCDC3: Built-in 1 Booster ON/OFF (Initial status) rd - DCDC3= 0: 3 Booster OFF (Initial status) rd - DCDC3= 1: 3 Booster ON 29 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation Set (28H) This Instruction sets up the driving voltage slope for temperature compensation. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 0 0 1 0 0 0 0 1 0 0 0 1 0 DB2 0 0 DB1 0 TCS DB0 0 TCS: Temperature compensation slope set TCS = 00 : 0.00%/degC TCS = 01 : -0.05%/degC TCS = 10 : -0.10%/degC TCS = 11 : -0.15%degC 00: 0.00 %/degC Driving voltage 01: -0.05 %/degC 10: -0.10 %/degC 11: -0.15 %/degC Temperature 30 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation If external temperature compensation is needed, circuit diagram is described as below. To use temperature compensation, two resistors and one thermistor are needed. Internal Chip External V1-i + - V1-o V1-t INTRS 31 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Contrast Control (1) (2AH) This instruction updates the contrast control value in normal display mode and partial display mode 0. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 1 0 0 1 0 1 0 1 Contrast control value (0 to 255) DB0 0 The relation between V1 voltage (typ.) and Contrast(1) set value ( 3bit step case) Contrast(1) Contrast(1) Contrast(1) Contrast(1) Contrast(1) V1[V] V1[V] V1[V] V1[V] V1[V] (HEX) (HEX) (HEX) (HEX) (HEX) 00h 2.000 30h 2.244 60h 2.488 90h 2.731 C0h 2.975 08h 2.041 38h 2.284 68h 2.528 98h 2.772 C8h 3.016 10h 2.081 40h 2.325 70h 2.569 A0h 2.813 D0h 3.056 18h 2.122 48h 2.366 78h 2.609 A8h 2.853 D8h 3.097 20h 2.163 50h 2.406 80h 2.650 B0h 2.894 E0h 3.138 28h 2.203 58h 2.447 88h 2.691 B8h 2.934 E8h 3.178 Contrast(1) (HEX) F0h F8h FFh V1[V] 3.219 3.259 3.300 Contrast Control (2) (2BH) This instruction updates the contrast control value in partial display mode 1. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 0 0 1 0 0 0 1 0 DB2 0 DB1 0 DB0 1 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(2) set value ( 3bit step case) Contrast(1) (HEX) 00h 08h 10h 18h 20h 28h V1[V] 2.000 2.041 2.081 2.122 2.163 2.203 Contrast(1) (HEX) 30h 38h 40h 48h 50h 58h V1[V] 2.244 2.284 2.325 2.366 2.406 2.447 Contrast(1) (HEX) 60h 68h 70h 78h 80h 88h V1[V] 2.488 2.528 2.569 2.609 2.650 2.691 Contrast(1) (HEX) 90h 98h A0h A8h B0h B8h V1[V] 2.731 2.772 2.813 2.853 2.894 2.934 Contrast(1) (HEX) C0h C8h D0h D8h E0h E8h V1[V] 2.975 3.016 3.056 3.097 3.138 3.178 Contrast(1) (HEX) F0h F8h FFh V1[V] 3.219 3.259 3.300 32 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Standby Mode OFF (2CH) This instruction releases the standby mode. D/I 0 /WR 0 /RD 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 0 The internal statuses during standby off are as following: All common and segment output: refer to following Oscillator circuit: On (EXT = 0, OSC=1),OFF (others) Displaying clocks (FR, PM, CL, CK): In operation Function and Pin condition at standby OFF Function/Pin DC/DC booster(1'st,2'nd,3'rd) COM outputs SEG outputs Condition ON(Operate) +VR /VM / VSS /-VR V1 /VSS Standby Mode ON (2DH) This instruction enters the standby mode to reduce the power consumption to the static power consumption value (Initial status). The following instructions, standby off and display on, cause returning to the normal operation status. D/I 0 /WR 0 /RD 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 1 The internal statuses during standby on are as following: All common and segment output: refer to following table Oscillator circuit: OFF Displaying clocks (FR, PM, CL, CK) are held. Function and Pin condition at standby ON Function/Pin DC/DC booster(1'st,2'nd,3'rd) SEG and COM outputs Condition OFF VSS LCD driving power output condition at Standby ON. Level +VR V1 VM -VR Condition VSS VSS VSS VSS 33 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Addressing Mode Set (30H) D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 0 0 DB5 1 GSM DB4 1 DSG DB3 0 SGF DB2 0 SGP DB1 0 DB0 0 SGM GSM: Gray Scale Mode 0 : 4,096 Color mode(Initial status) 1 : 256 Color mode 1. 8 bit mode : DB[7:0] :RRRGGGBB 2.16bit mode: DB[15:0] :RRRGGGBBRRRGGGBB 3. 3bits of R and G, 2bits of B are expanded to 4 bit internally by red, green and blue palette set instruction DSG : Duty Adjust Setting 0 : Dummy subgroup is one subgroup (Initial status) 1 : Dummy subgroup is none SGF : SG Frame Inversion mode setting 0: SG Frame inversion OFF (Initial status) 1: SG Frame inversion ON SGM : SG inversion mode setting 0: SG inversion OFF (Initial status) 1: SG inversion ON SGP : SG Phase mode setting 00 : Same phase in all pixels 01 : Different phase by 1pixel-unit 10 : Different phase by 2pixel-unit 11 : Different phase by 4pixel-unit Row Vector Mode Set (32H) Setting ROW function. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 0 DB5 1 0 DB4 1 0 DB3 0 DB2 0 INC DB1 1 DB0 0 VEC INC: Row Vector Increment Mode. This Parameter set up Row vector increment period DB3 0 0 0 0 1 1 1 1 DB2 0 0 1 1 0 0 1 1 DB1 0 1 0 1 0 1 0 1 Row Vector Increment Period Every subgroup Every 2subgroup Every 4subgroup Every 8subgroup Every 16subgroup Every 16subgroup Every 16subgroup Every subframe VEC: ROW Vector Sequence Mode - 0: R1->R2->R3->R4 -> R1..... (initial status) - 1: R1->R3->R2->R4 -> R1..... 34 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD N-block inversion Set (34H) This instruction set up N block inversion for AC driving. D/I /WR /RD DB7 DB6 DB5 0 0 1 0 FIM 0 FIP 0 0 DB4 1 DB3 1 DB2 1 N-block inversion DB1 1 DB0 1 FIM: Forcing Inversion Mode FIM = 0: Forcing Inversion OFF (Initial status) FIM = 1: Forcing Inversion ON FIP: Forcing Inversion Period FIP = 0: Forcing Inversion Period is one frame FIP = 1: Forcing Inversion Period is two frames N-block Inversion : This parameter indicates the basic period of polarity inversion. The whole period of polarity inversion is decided by FIM, FIP and this parameter. DB7 X 0 : 0 1 : 1 1 : 1 DB6 x x : x 0 : 0 1 : 1 DB5 x x : x x : x x : x DB4 - DB0 0 1 : 31 1 : 31 1 : 31 every frame every 1 block : every 31 blocks every 1 block and every frame : every 31 blocks and every frame every 1 block and every 2 frames : every 31 blcks and every 2 frames Polarity Inversion Period 35 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Red palette Set (38H) Setting red gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB5 1 0 0 0 0 0 0 0 0 DB4 1 0 0 0 0 0 0 0 0 DB3 1 DB2 0 DB1 0 DB0 0 RAM data "000" to GS data RAM data "001" to GS data RAM data "010" to GS data RAM data "011" to GS data RAM data "100" to GS data RAM data "101" to GS data RAM data "110" to GS data RAM data "111" to GS data Green palette Set (3AH) Setting green gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB5 1 0 0 0 0 0 0 0 0 DB4 1 0 0 0 0 0 0 0 0 DB3 1 DB2 0 DB1 1 DB0 0 RAM data "000" to GS data RAM data "001" to GS data RAM data "010" to GS data RAM data "011" to GS data RAM data "100" to GS data RAM data "101" to GS data RAM data "110" to GS data RAM data "111" to GS data Blue palette Set (3CH) Setting blue gray scale data for 256 Color mode. D/I /WR /RD DB7 0 0 0 0 1 0 0 0 DB6 0 0 0 0 0 DB5 1 0 0 0 0 DB4 1 0 0 0 0 DB3 1 DB2 1 DB1 0 DB0 0 RAM data "000" to GS data RAM data "001" to GS data RAM data "010" to GS data RAM data "011" to GS data 36 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Entry Mode Set (40H) Setting internal function mode. D/I /WR /RD 0 0 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 0 HL DB1 0 X/Y DB0 0 RMW HL: Exchange higher and lower byte only for "Display Data Write/Read" in 256 color & 16-bit data bus . HL = 0 : Exchange status(initial status) HL = 1 : Not exchange status X/Y: Memory address counter mode setting X/Y = 0: Y address counter mode (Initial status) X/Y = 1: X address counter mode (Don't use in 256 color & 16bit data bus mode) RMW: Read modify write mode ON/OFF select RMW = 0: Read modify write OFF (Initial status) RMW = 1: Read modify write ON. When this mode is on, X(Y) address of on-chip display RAM is increment not in reading display data but in writing display data. X Address Area Set (42H) This instruction and parameter set up the X address areas of the on-chip display data RAM. D/I 0 /WR 0 /RD 1 DB7 0 0 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 X start address set (Initial Status = 00H) X end address set (Initial Status = 7FH) The current X address of the on-chip display data RAM is the X start address by setting this instruction. In X address count mode (X/Y = "H"), the X address is increased from X start address to X end address. When X address is equal to the X end address, the Y address is increased by 1 and the X address returns to X start address. The X start and X end addresses must be set as a pair and X start address must be less than X end address. Address Area Set (43H) This instruction and parameter set up the Y address areas of the on-chip display data RAM. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 1 0 0 1 0 0 0 0 DB1 1 DB0 1 Y start address set (Initial Status = 00H) Y end address set (Initial Status = 7FH) The current Y address of the on-chip display data RAM is the Y start address by setting this instruction. In Y address count mode (X/Y = "L"), the Y address is increased from Y start address to Y end address. When Y address is equal to the Y end address, the X address is increased by 1 and the Y address returns to Y start address. The Y start and Y end address must be set as a pair and Y start address must be less than Y end address. 37 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display OFF (50H) Turn the display OFF(Initial status). When display is off, all segment and common output are VSS level. D/I 0 /WR 0 /RD 1 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 0 Function and Pin condition at Display OFF Function/Pin DC/DC booster(1 ,2 ,3 ) SEG and COM outputs st nd rd Condition ON(Operate) VSS Display ON (51H) Turns the display ON. In case of being standby mode, this instruction does not work. This instruction is executed after standby mode off. D/I 0 /WR 0 /RD 1 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 1 Function and Pin condition at Display ON Function/Pin Condition DC/DC booster(1 ,2 ,3 ) COM outputs SEG outputs st nd rd ON(Operate) +VR /VM /-VR V1 /VSS Specified Display Pattern Set (53H) This instruction sets the specified display pattern. D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 1 0 DB3 0 0 DB2 0 0 DB1 1 SDP DB0 1 SDP : Specified Display Pattern set - SDP = 00 : Normal display - SDP = 01 : Reverse display : Display data reversing mode setting without the contents of the display RAM SDP = 10 : Whole display pattern becomes OFF regardless of the RAM data. SDP = 11 : Whole display pattern becomes ON regardless of the RAM data. 38 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode Set (55H) D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 1 0 DB3 0 0 DB2 1 0 DB1 0 PDM DB0 1 PT PT: Partial Display ON/OFF PT = 0: Partial display OFF = Normal mode (Initial status) PT = 1: Partial display ON PDM: Partial Display mode set PDM = 0: Partial mode 0 : Duty ratio is same as Normal display mode(initial status) PDM = 1: Partial mode 1 : Duty ratio is changed from Normal display mode(66 duty fixed) Applied parameter in PDM0 and PDM1 are summarized as below PDM 0 1 Contrast Contrast control(1) Contrast control(1) Duty Normal 1/66 Bias Bias(1) Bias(2) DC-DC Select DC-DC(1),DC(1) DC-DC(1),DC(2) OSC OSC1-OSC2 OSC3-OSC4 PCK DIV(1) DIV(2) Partial Start Line Display Area N line Partial Start Line M line Partial End Line Max. 66 line Partial End Line PDM 0 No display Area PDM 1 : No COM Scanning field (COM = Vm fixed) Except Partial Display Area : COM Timing is existing, but COM = Vm fixed Partial Display Area : Real display field Operation in Partial Display Mode 0 (PDM=0) On scanning except partial display area -SEG output select V0 or V1 level depend on "FR" value. Refer to 44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode Operation in Partial Display Mode 1 (PDM=1) Display area is from partial start line to partial end line. (COM driver output is fixed VM except display area, only max66 line output COM signal. On scanning except partial display area -SEG output select V0 or V1 level depend on "FR" value. Refer to Page44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode 39 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode0 In case of COM 6 to COM11 Partial display +VR VM -VR Normal Display Mode Partial Display Mode 0 Item Duty Contrast Oscillator SEG Output level COM Output level Partial Display Area Out of Partial Display Area Same as normal display mode Same as normal display mode ( Contrast(1) setting ) Same as normal display mode ( OSC1 - OSC2 ) Same as normal mode (V1,V0) Same as normal mode (+VR,VM,-VR) Depends on Internal "FR" signal See page 44 VM fixed 40 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial display mode1 In case of COM 6 to COM11 Partial display +VR VM -VR Normal Display Mode Partial Display Mode 1 Item Duty Contrast Oscillator SEG Output level COM Output level Partial Display Area Out of Partial Display Area 1/66duty Contrast(2) setting ( OSC3 - OSC4 ) setting value Out of Display Area Same as normal mode (V1,V0) Same as normal mode (+VR, VM, -VR) Depends on "FR" signal See page 44 VM fixed VM fixed 41 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Start Line Set (56H), Partial Display End Line Set(57H) These 2 instructions set the partial display area and it is possible to display a part. Partial Display Start Line Set (56H) D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 Partial start line DB2 1 DB1 1 DB0 0 Partial Display End Line Set (57H) D/I 0 /WR 0 /RD 1 DB7 0 0 DB6 1 DB5 0 DB4 1 DB3 0 Partial end line DB2 1 DB1 1 DB0 1 COM 0 COM 1 COM 2 COM 3 line 0 line 1 line 2 line 3 : : : line 126 line 127 line 128 COM 126 COM 127 COM 128 Parameter set appoints display line number. At PDM 0, Parameter Size is able to be in a number of Display lines. But that is not able to be over max 66 line at PDM 1. Partial end line must set bigger number than Partial start line. 42 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Example of Segment Voltage in non-display area Frame Subframe N 0 VM Display Off Partial Display Addressing Duty N+1 2 3 VM VM 1 VM 0 +VR COM VM -VR internal polarity counter (FR) V1 V1 V0 V0 V1 V1 V0 V1 V0 V1 V0 SEG V0 43 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Area scroll Set (59H) This instruction sets up area scroll field (start line, end line, Lower fixed line number), and it is possible to make screen to display as partial scroll field. D/I /WR /RD DB7 0 0 0 0 1 0 0 0 DB6 1 0 DB5 0 0 DB4 1 0 DB3 1 0 DB2 0 0 DB1 0 SCM DB0 1 Scroll area start line Scroll area end line Lower fixed number Note: In lower and center scroll mode, scroll area end line must be smaller than duty - lower fixed number. SCM: Scroll mode setting DB1 0 0 1 1 DB0 0 1 0 1 Mode Entire display(Initial status) Upper scroll display Lower scroll display Center scroll display Entire Display Upper Display Lower Display Center Display 44 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Scroll Start Line Set (5AH) This instruction and parameter set up scroll start line. On this instruction, scroll start line becomes the first of area scroll field. Scroll operation is occurred every issue of this instruction. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 1 0 1 1 Scroll start line 0 1 0 Addr0 Addr5 Addr40 Xadr=40 Scroll display Scroll area Addr119 Addr6 COM120 COM127 Lower fix Xadr=120 Xadr=127 Lower fix COM120 COM127 Addr39 Addr120 Addr127 RAM Address. 45 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Normal Mode Set partial start line Set partial end line Set partial mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line Set scroll start line Set partial start line Set partial end line Set partial mode 0 Partial Mode 0 Scroll Mode Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Scroll/Partial Mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Release partial mode Release partial mode Normal Mode Data Format Select (60H/61H) D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 DFS DFS: 4,096 Color Mode Data Format Select - 0 : 4,096 Color Data Format A (Initial Status) 8 bit mode : DB[7:0] : XXXXRRRR (1'st write) DB[7:0] : GGGGBBBB(2'nd write) 16 bit mode : DB[15:0] :XXXXRRRRGGGGBBBB (12 bit) - 1 : 4,096 Color Data Format B 8 bit mode : DB[7:0] : RRRRGGGG(1'st write) DB[7:0] : BBBBRRRR (2'nd write) DB[7:0] : GGGGBBBB(3'rd write) 16 bit mode : DB[15:0] :RRRRGGGGBBBBXXXX (12 bit) 46 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display Data Write/Read D/I 1 1 /WR 0 1 /RD 1 0 DB15 ~ DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display RAM write in data Display RAM read out data 1. 4,096 Color mode (1) 16bit access mode 15 1 cycle nd st 14 X X 6 X G2 X G2 13 X X 5 X G1 X G1 12 X X 4 X G0 X G0 11 R3 R3 3 R3 B3 R3 B3 10 R2 R2 2 R2 B2 R2 B2 9 R1 R1 1 R1 B1 R1 B1 8 R0 R0 0 R0 B0 R0 B0 7 G3 G3 6 G2 G2 5 G1 G1 4 G0 G0 3 B3 B3 2 B2 B2 1 B1 B1 0 B0 B0 X 2 cycle X (2) 8bit access mode 7 1 cycle 2 nd rd th st X G3 X G3 cycle cycle 3 4 cycle 2. 256 color mode (1) 16bit access mode 15 1 cycle R2 (3) 8bit access mode 7 1 cycle st st 14 R1 6 R1 13 R0 5 R0 12 G2 4 G2 11 G1 3 G1 10 G0 2 G0 9 B1 1 B1 8 B0 0 B0 7 R2 6 R1 5 R0 4 G2 3 G1 2 G0 1 B1 0 B0 R2 Status Read D/I 0 /WR 1 /RD 0 DB7 BSY DB6 X/Y DB5 0 DB4 PDM DB3 PT DB2 STB DB1 REV DB0 DP This instruction indicates the internal status of the S6B33A2. DP: ( 0 : Display OFF Status, 1 : Display ON Status ) REV: ( 0 : Display Image Non-Reversing, 1 : Display Image Reversing ) STB: ( 0 : Standby Mode OFF Status, 1 : Standby Mode ON Status ) PT: ( 0 : Partial Display Mode OFF Status, 1 : Partial Display Mode ON Status ) PDM: ( 0 : Partial Display Mode 0, 1 : Partial Display Mode 1 ) X/Y: ( 0 : Y-address Count Mode, 1 : X-address Count Mode ) BSY: ( 0 : No Busy, 1 : Busy ) 47 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Set Display Data Length This Instruction is only used in 3-pin SPI MPU interface mode(PS="L", MPU[1]="L"). It consists of two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second and third bytes will be number of data bytes will be write. When DI is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. D/I 0 /WR 0 /RD 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0 Number of display data upper 8bits (DDL_H) Number of display data lower 8bits (DDL_L) Test Mode1 (FFH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I 0 Test Mode2 (FEH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 0 0 1 1 1 1 1 1 1 DB1 1 DB0 0 /WR 0 /RD 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 1 48 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INSTRUCTION PARAMETER Table 16. Instruction Parameter Instruction Oscillation Mode Set Driver Output Mode Set DC-DC Set PCK Generation Mode Set DCDC and AMP ON/OFF Set Temperature Compensation Set Contrast Control (1) Contrast Control(2) Addressing Mode Set ROW Vector Mode Set N-line Inversion Set Hex 02H 10H 20H 24H 26H 28H 2AH 2BH 30H 32H 34H Para. 1 1 1 1 1 1 1 1 1 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 EXT OSC * * * * * * 0 0 0 0 0 0 0 0 SDIR SWP * * * * * * 0 0 0 0 0 0 0 0 DC(2) DC(1) 0 0 0 0 0 0 0 0 0 0 DIV(2) 0 0 DIV(1) * * 1 0 * * 1 0 0 0 0 0 AMP DCDC3 DCDC2 DCDC1 * * * * 0 0 0 0 0 0 0 0 0 0 TCS * * * * * * 0 0 Contrast control value in normal and partial display mode0(0 to 255) 0 0 0 0 0 0 0 0 Contrast control value in partial display mode 1(0 to 255) 0 0 0 0 0 0 0 0 0 GSM DSG SGF SGP SGM 0 * * 0 0 0 0 0 0 0 0 0 0 INC VEC * * * * 0 0 0 0 FIM FIP 0 N-block Inversion 0 0 * 0 0 0 0 0 0 0 0 0 RAM data "000" to GS data 0 0 0 0 RAM data "001" to GS data 0 0 0 0 RAM data "010" to GS data 0 0 0 0 RAM data "011" to GS data 0 0 0 0 RAM data "100" to GS data 0 0 0 0 RAM data "101" to GS data 0 0 0 0 RAM data "110" to GS data 0 0 0 0 RAM data "111" to GS data 0 0 0 0 RAM data "000" to GS data 0 0 0 0 RAM data "001" to GS data 0 0 0 0 RAM data "010" to GS data 0 0 0 0 RAM data "011" to GS data 0 0 0 0 RAM data "100" to GS data 0 0 0 0 RAM data "101" to GS data 0 0 0 0 RAM data "110" to GS data 0 0 0 0 RAM data "111" to GS data 0 0 0 0 RAM data "000" to GS data 0 0 0 0 RAM data "001" to GS data 0 0 0 0 RAM data "010" to GS data 0 0 0 0 RAM data "011" to GS data 0 0 0 0 0 HL X/Y RMW * * * * * 0 0 0 0 X Start address set * 0 0 0 0 0 0 0 0 X end address set * 1 1 1 1 1 1 1 0 Y start address set * 0 0 0 0 0 0 0 0 Y end address set * 1 1 1 1 1 1 1 Red palette Set 38H 8 Green palette Set 3AH 8 Blue palette Set 3CH 4 Entry Mode Set 40H 1 X-address Area Set 42H 2 Y-address Area Set 43H 2 49 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Set Display Data Length Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set FCH 53H 55H 56H 57H 2 1 1 1 1 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 0 0 * 0 1 0 0 Number of display data upper word Number of display data lower word 0 0 0 0 SDP * * * * 0 0 0 0 0 0 PDM PT * * * * 0 0 Partial start line 0 0 0 0 0 0 Partial end line 0 0 0 0 0 0 0 0 0 0 SCM * * * * 0 0 Scroll area start line 0 0 0 0 0 0 Scroll area end line 1 1 1 1 1 Lower Fixed number 0 0 0 0 0 0 Scroll start line 0 0 0 0 0 0 Area Scroll Mode Set 59H 4 Scroll Start Line Set 5AH 1 50 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Reset Operation When /RST becomes "L", following procedure is occurred. - X address: 0 - Y address: 0 - Display OFF - Read Modify Write Mode OFF - Function Mode Set OSC = 0: Oscillator OFF EXT = 0: Internal Oscillator Mode REV = 0: Reversing mode OFF X/Y = 0: Y-address Count Mode HL = 0 Standby Mode ON - PCK Generation mode Set DIV(1) = 10: fPCK = fOSC/6x DIV(2) = 10: fPCK = fOSC/6x - DC-DC Select DC(1) = 0: X1 step-up DC(2) = 0: X1 step-up - DC/DC and AMP ON/OFF Set AMP =0: Built-in OP-AMP OFF st DCDC1 =0: Built-in 1 booster OFF nd DCDC2 =0: Built-in 2 booster OFF rd DCDC3 =0: Built-in 3 booster OFF - N-block inversion FIM =0: Forcing Inversion OFF FIP =0: Forcing Inversion Period in one frame N-block inversion = 00H: frame inversion - Partial Display Mode PT = 0: Partial Display Mode OFF PDM = 0: Partial Mode 0 - Partial Display Area Set Partial start line = 00H Partial end line = 00H -Area Scroll Set Mode = 00H : Entire Display Scroll Mode Area Start Line: 00H Area End Line: 7FH Lower Fixed Line Number: 00H - Scroll Start Line Set Scroll Start Line: 00H - Addressing Mode Set GSM =0: 4,096 color mode DSG = 0: Mode 0 SGF = 0: SG Frame Inversion OFF SGM = 0: SG Reverse Mode OFF SGP=00:Same phase in all pixel 51 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Item Supply Voltage range LCD Supply Voltage range Input Voltage range Operating Temperature range Storage Temperature range Symbol VDD |VCC - VEE| Vin TOPR TSTR - 0.3 to -0.3 Rating to 20 VDD +0.3 +4.0 Unit V V V C C -30 to +70 -55 to +150 OPERATING VOLTAGE Item Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Symbol VDD 2Vr VIN Min. 1.8 2.4 Typ. 3.0 Max. 3.3 20 3.6 Unit V V V 52 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (1) (Vss = 0V, VDD = 1.8 to 3.3V, Ta = -30 to 70 C) Item Operating voltage Operating voltage Operating voltage Operating voltage Operating voltage Operating voltage Symbol VDD VIN1 DC2IN VIN2 VIN45 2Vr VM Driving voltage input range VCC VEE Input voltage High Low Output voltage High Low Input leakage current Output leakage current Oscillator Frequency Tolerance Normal or Partial 0 Partial 1 Normal or Partial 0 Partial 1 VIH VIL VOH VOL IIL IOZ FOSC1 IOH = 0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS R1=? (fFR=80Hz target), DSG=0, 128 display lines R1=? (fFR=80Hz target), DSG=0, 66 display lines (*1) External power supply mode 2Vr = |(+VR)- (-VR)| Condition Min 1.8 2.4 1.66 2.4 2.4 4.0 1.0 7.0 -8.25 0.8VDD VSS 0.8VDD VSS -1.0 -3.0 50.688 56.32 Typ Max 3.3 3.6 2.75 5.4 5.4 20 1.65 11.55 -5.0 VDD 0.2VDD VDD 0.2VDD +1.0 +3.0 61.952 A A kHz OSC1 - OSC2 OSC3 - OSC4 OSC1 - OSC2 OSC3 - OSC4 V Unit V V V V V V V V V V Remarks VDD VCI DC2IN VIN2 VIN45 +VR, -VR VM VCC VEE FOSC2 26.496 29.44 32.384 kHz Oscillator Frequency Range FOSC1 35.200 70.400 kHz FOSC2 V1 VM (*2) 18.400 2.0 1.0 - 36.800 3.3 1.65 kHz V Driving voltage input range (*1) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=128 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=128 (*2) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=66 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=66 53 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (2) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Item SEG Driver output resistance COM RON-Com Symbol RON-Seg Condition V1=3.3 V, VM=1.65V, V0=0V, Ta = 25C, Iload=100uA VCC=12 V, VM=1.5V, VEE=-9.0V, Ta = 25C, Iload=100uA VDD=3V VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD=1.8V VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD=3V VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern VDD=1.8V VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern Min Typ 1.5 Max 3.0 Unit k Remarks SEGn - 1.0 1.5 k COMn - 400 - Normal Mode IDD1 - 270 - Current consumption VDD - 240 - Partial1 Mode IDD2 - 180 - * : "IDD1 and IDD2" are determined from lowest power consumption for dc-dc converter. 54 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (3) Item Symbol (+VR) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Condition Min Typ Max Unit Remarks Low current mode Isource = 80uA High current mode Isource = 150 or 250uA Low current mode Isource = 250uA High current mode Isource = 500 or 1000uA Low current mode Isource,sink = 250uA High current mode Isource,sink = 500 or 1000uA Low current mode Isink = 80uA High current mode Isink = 150 or 250uA 100 mV +VR (V1) Voltage shift range(*1) (VM) - - 20 mV V1 - - 20 mV VM (-VR) - - 100 mV -VR (*1) Voltage shift means output voltage deference between output current = Iload and no-load. Refer to the following figure. (in case of source current mode) No-load Vx Vx Current = I Load Vy I=0 Vshift = |Vx-Vy| Vy I=ILoad Item Tolerance of Bias ratio Symbol (+VR)_0 (-VR)_0(*1) Condition No load Min -100 Typ - Max +100 Unit mV Remarks +VR -VR (*1) Tolerance of bias ratio definition (+VR)_0 = ((+VR) - VM ) - VM *6 (-VR)_0 = ( VM - (-VR)) - VM *6 55 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (4) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Item Temperature compensation Tolerance of Contrast step of V1 Symbol Vt Vstep Contrast set = FFh Contrast set = 00h V1 VM V1 VM Condition VDD=VIN1=V1=3.0V, -20 to 70 C Min -0.02 2.539 3.25 1.60 1.95 0.95 Typ 5.078 3.3 1.65 2.00 1.00 Max +0.02 7.617 3.35 1.70 2.05 1.05 Unit %/C mV V V V V Remarks V1 V1 V1 VM V1 VM Voltage range V1 VM Item ||+VR-VM| -|VM -(-VR)|| Offset Voltage A ||V1-VM| -|VM-V0|| B Condition Load current Voltage range Max 100 Unit mV Ref Fig.1 I Load = +100uA (+VR) I Load = -100uA (-VR) I Load = +100uA ( V1, VM ) I Load = +100uA (+VR) I Load = -100uA (-VR) +VR=7.0~11.55 V V1=2.0~3.3V VM=1.0~1.65V -VR=-8.25~-5 V 50 mV Fig.2 +VR Vx VM Vy -VR +100uA V1 Va +100uA (both Case A and B) -100uA (Case B) +100uA (Case A) Vb |Vx-Vy| < 100mV VM -100uA V0 |Va-Vb| < 50mV Fig. 1: Offset voltage definition (+VR,VM,-VR) Fig. 2: Offset voltage definition (V1,VM,V0) 56 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (5) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Range Min V1OUT Voltage Level VMOUT DC2OUT (*1) This definition is shown as below VIN45 A V V1OUT A V > 0.3 V (External VIN45) A V > 0.5 V (VIN45 = VOUT45) If V1OUT input voltage is set over VIN45, V1OUT output voltage must be clipped near VIN45. In this case, V1OUT output level must not be unstable. Refer to Fig.1 VIN45 VIN45 - AV Fig. 1 V1OUT Input Item Max (DC(1) and DC(2) = X1.5) 3.3 V(*1) 1.65 V(*2) 2.75 V(*3) V1OUT Output VIN45 2.0 V 1.0 V 1.67 V (*2) This definition is shown as below VIN1 A V VMOUT A V > 0.3 V If VMOUT input voltage is set over VIN1, VMOUT output voltage must be clipped near VIN1. In this case, VMOUT output level must not be unstable. Refer to Fig.2 (*3) This definition is shown as below VIN2 A V DC2OUT A V > 0.3 V (External VIN2) A V > 0.5 V (VIN2 = VOUT45) If DC2OUT input voltage is set over VIN2, DC2OUT output voltage must be clipped near VIN2. In this case, VMOUT output level must not be unstable. Refer to Fig.3 VMOUT Output VIN1 VIN1 VIN1 - AV Fig. 2 VMOUT Input DC2OUT Output VIN2 VIN2 - AV VIN2 DC2OUT Input Fig.3 57 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) D/I tAS80 /CS1 (CS2) tPW L80(R), /RD, /WR 0.9V DD 0.1V DD tDS80 DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and /WR(/RD) is low. Figure 27. Parallel Interface (8080-series MPU) Timing Diagram Table 17. AC Characteristics (8080-series Parallel Mode) Item Address setup time Address hold time System cycle time Pulse width low for write Pulse width High for write Pulse width low for read Pulse width high for read Data setup time Data hold time Read access time Output disable time /WR (/WR) /RD (/RD) DB0 to DB15 Signal D/I Symbol tAS80 tAH80 tCY80 tPWLW tPWHW tPWLR tPWHR tDS80 tDH80 tACC80 tOD80 Condition 1.8V/3.3V 1.8V/3.3V 1.8V 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V CL = 100 pF (VDD = 1.8 to 3.3V, Ta = -30 to +70C) Min. Max. Unit 0 0 470 180 160 70 160 70 70/35 15/10 170/90 ns ns tOD80 tDH80 tPWL80(W) tCY80 tPWH80(R), tPW H80(W) tAH80 ns ns ns ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read 58 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Read / Write Characteristics (6800-series Microprocessor) D/I,R/W tAS68 tAH68 /CS1 (CS2) tEW H68(R), tEWH68(W) tCY68 t EWL68(R), tEWL68(W) E 0.1VDD 0.9VDD tDS68 tDH68 DB0 to DB7 (Write) tACC68 tOD68 DB0 to DB7 (Read) ** tEWH68(W) and t EWH68(R) is specified in the overlapped period when /CS1 is low (CS2 is high) and E is high. Figure 28. Parallel Interface (6800-series MPU) Timing Diagram Table 18. AC Characteristics (6800-series Parallel Mode) (VDD = 1.8 to 3.3V, Ta = -30 to +70C) Item Address setup time Address hold time System cycle time Enable width high for write Enable width low for write Enable width high for read Enable width low for read Data setup time Data hold time Read access time Output disable time /RD (E) /RD (E) DB0 to DB15 Signal D/I R/W Symbol tAS68 tAH68 tCY68 tEWHW tEWLW tEWHR tEWLR tDS68 tDH68 TACC68 tOD68 Condition 1.8V/3.3V 1.8V/3.3V 1.8V 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V CL = 100 pF Min. 0 0 470 180 160 70 160 70 70/35 15/10 170/90 Max. Unit ns ns ns ns ns ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read 59 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Serial Data Interface Timing /CS1 (CS2) 0.1VDD t CSS t SCYC t CSH 0.1VDD tr tSHW tSLW SCL tf t SAS tSAH D/I t SDS tSDH 0.9VDD 0.1VDD 0.9VDD 0.1VDD SDI Table 19. Serial Data Interface Timing (VDD = 1.8 to 3.3V, Ta = -30 to +70C) Item SCL Cycle Time SCL High Pulse Width SCL Low Pulse Width SDI Setup time SDI Hold time D/I Setup time D/I Hold time Chip Select Setup time Chip Select Hold time Signal SCL SCL SCL SDI SDI D/I D/I /CS1 (CS2) /CS1 (CS2) Symbol tCSC tSHW tSLW tSDS tSDH tSAS tSAH tCSS tCHS Condition Min. 50 20 20 20 20 20 20 20 20 Max. Unit us ns ns ns ns ns ns ns ns 60 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Reset Input Timing tRW /RST tR Internal status During reset Reset complete Figure 29. Reset Input Timing Diagram Table 20. AC Characteristics (Reset mode) (VDD = 1.8 to 3.3V, Ta = -30 to +70C) Item Reset low pulse width Reset time Signal /RST Symbol tRW tR Condition Min. 1000 Max. 1000 Unit ns ns 61 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SYSTEM APPLICATION DIAGRAM Internal Power Mode External Components VDD VDD or REG_OUT C1 VDD1 REG_OUT Name R1,R2 C1,C2,C3 D1 Device Resistors Capacitors Schottky barrier diode VSS Values of external Capacitors and D1 Item Capacitance 1.0 to 4.7F 1.0 to 2.2F 1.0 to 2.2F Vforward = Max. 0.3V at 1mA Vreverse = Min. 15V DB15DB0 /RD DB15 to DB0 /RD /WR /CS1 CS2 D/I MPU /WR /CS1 CS2 D/I C1 C2 C3 D1 R1 OSC1 R2 OSC2 OSC3 OSC4 OSC5 Maximum rating voltage of capacitors Maximum Item rating voltage REG_OUT to VSS VOUT45 to VSS C11P to C11M C12P to C12M VMOUT to VSS DC2OUT to VSS V1OUT to VSS C21P to C21M C22P to C22M C23P to C23M VSS to VRN C31P to C31M VRP to VSS VIN2 VIN2 DC2OUT DC2IN C21P C21M C22P C22M C2 C2 C2 C3 S6B33A2 VIN1 VIN1 C2 C2 C11P C11M C12P C12M VOUT45 C3 VIN45 3V 8V 6V 6V 3V 5V 6V 5V 10V 13V 13V 17V 18V V1OUT C3 V1IN C23P C23M VRN VEE VMOUT C3 VMIN C3 C31P V0IN C31M VRP VCC C3 C2 62 S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD External Power Mode VDD VDD1 REG_OUT C VDD or REG_OUT VSS DB15 to DB0 /RD DB15 to DB0 /RD /WR /CS1 CS2 D/I MPU /WR /CS1 CS2 D/I R1 OSC1 OSC2 OSC3 OSC4 OSC5 R2 VIN1 VIN1 C11P C11M C12P C12M VOUT45 VIN45 S6B33A2 00 VIN2 VIN2 DC2OUT DC2IN C21P C21M C22P C22M C23P C23M V1IN V1OUT V1IN VRN VMOUT VMIN VEE VEE VMIN V0IN C31P C31M VRP VCC VCC 63 |
Price & Availability of S6B33A2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |